1. Field of the Invention
The present invention relates to a storage device including a nonvolatile memory and a computer system and, more specifically, to a storage device whose main storage medium is a flash memory, a computer system, and a storage device access method.
2. Description of the Related Art
In recent years, flash memories have been receiving attention as a storage medium for use for digital still cameras or mobile computer equipment.
The flash memory is a semiconductor memory for storing therein data. For data storage, by using electron tunneling or acceleration of hot electrons, electrons are injected to a floating gate or a trapping layer after being made to pass through a gate insulation film so that a threshold value of a cell transistor is changed. In such a semiconductor memory, only one transistor of a multilayer gate or MNOS (Metal Nitride Oxide Semiconductor memory) structure can configure a memory cell so that the resulting memory can be inexpensive and large in capacity.
For such a semiconductor memory, a NAND flash memory is typically exemplified.
FIG. 1 is a diagram showing an exemplary internal configuration of a NAND flash memory.
The NAND flash memory of FIG. 1 includes a plurality of memory units 1-1 to 1-n in an array (in length and width directions). The memory units 1-1 to 1-n are connected to bit lines BL1 to BLn, respectively.
For example, a gate of a selection transistor 2 is connected to a selection gate line SL1, and a gate of another selection transistor 3 is connected to a selection gate line SL2. Gates of memory cells N0 to N15 are connected to word lines WL0 to WL15, respectively.
The memory cells N0 to N15 are each of multilayer gate structure and store therein data in accordance with the amount of charge stored for a floating gate. That is, when many electrons are stored in the floating gate, a transistor is increased in threshold value. For an assessment of data, an access circuit 4 including a sense amplifier or others is used to detect whether there is a current flow from the charged bit lines BL1 to BLn to the memory units 1, i.e., 1-1 to 1-n. 
Such a NAND flash memory has no need to include an area for every memory cell to come in contact with the bit lines. In this sense, the NAND flash memory is considered suitable for use as a medium of inexpensive large-capacity storage devices.
The issue here is that the flash memory is generally considerably slow in program speed and requires several hundreds of micro (μ) seconds per cell. With the fact that no overwriting of data is possible, there is a need to erase data before running of a program, and this takes several m seconds. To deal with such a problem, many memory cells are subjected to parallel processing.
That is, writing of a memory cell group 5, i.e., a page unit, including cells all connected to the word line WL0 is performed in a batch all at once, and erasing of a cell block 6 configured by page groups each sharing a memory unit is performed in a batch all at once. Through such batch writing and erasing, the program is increased in transfer speed.
More specifically, Non-patent Document 1 (Digest of ISSCC2002, p 106, session 6.4) describes a NAND flash memory of 1 Gb, in which a page size is 2 kbytes, and an erase block size is 128 kB. That is, in a memory array, a memory cell group of 128 kbytes is erased in parallel, and a memory cell is programmed thereto in parallel for every 2 kbytes, thereby realizing the program transfer speed of 10 MB/s.
Also, in the field of NAND flash memory, the memory takes various internal configurations as a result of memory size reduction and a development of multilevel memory. However, accessing the memory is still the same, i.e., using a unit referred to as page for batch writing/reading and a unit referred to as block or erase block for batch erasing, and the block still includes a plurality of pages.
Alternatively, the memory device may include a plurality of flash memory chips and perform parallel writing by putting the chips into operation all at once. With this being the configuration, a group of pages in each of the chips serves as an actual page in the memory device, and the actual page serves as a unit for batch writing for the memory device. In this configuration, a group of erase blocks corresponding to each of the chips also serves as an actual erase block in the memory device, and the actual erase block serves as a unit for batch erasing in the memory device. As such, also in such a memory device, the actual erase block being a unit for batch erasing is configured to include a plurality of actual pages, each being an individual writing unit.
Moreover, with such varying internal configuration as a result of memory size reduction, and with some change observed in writing mechanisms, constraints are imposed on the pages in the blocks for the order of writing. That is, writing to the pages is made in the forward direction from low-order addresses to high-order addresses, and writing in the backward direction is prohibited. For example, once writing is made to some page, no writing is allowed any more to the page no matter if any low-order address in the same block is not yet through with writing.
Note that the pages for the NAND flash memory each generally have a backup area of 64 bytes with respect to an area for storing therein the user data of 2 kbytes, for example. The backup area can store therein various types of management data, e.g., parity bits, on the side of a system using the NAND flash memory. Writing to such a backup area is generally required to be made in one operation with writing to the user data area so that the writing operation is executed always as a set, i.e., executed both to the backup area and the user data area.
With a general file storage, the minimum write unit is a sector of 512B, which is used as a basis for random access. In this case, a command is issued to rewrite only a part of one page area, for example.
If random access as such is made using the above-described flash memory, however, any actual erase block area has to be entirely erased. If the actual erase block area includes any effective file in its not-yet-selected area, the file has to be protected from being lost.
FIG. 2 shows an example for such a data update. The procedure for the data update is as follows.
1. First of all, data of an entire actual erase block area 21 is read from a flash memory 20 to a buffer memory 23.
2. Next, in the buffer memory 23, any corresponding data is updated.
3. The block area 21 on the flash memory is erased.
4. Lastly, from the buffer memory 23, updated block data is entirely written back to the data-erased area 21.
As such, a sequence of operations for rewriting a few sectors requires a huge overhead of reading and writing of data whose amount is about 100 times as large as the amount of data in the sectors and erase blocks. As a result, it takes a longer time to fully seek a hard disk drive.
For a file update, it is actually common to update, at the same time, not only any corresponding file but also a plurality of small areas related to the file, e.g., a management domain or a log description. There may be a case where a file itself is fragmented and scattered in a plurality of small areas. Therefore, if there are constraints as described above, the actual transfer capability will be considerably poor.
For the aim of increasing the efficiency of such a sequence of operations, more flexible memory management using address conversion has been variously proposed. The current most popular management is of performing address conversion on an erase block basis.
FIGS. 3A and 3B are diagrams both showing an exemplary method of performing address conversion on an erase block basis.
FIG. 3A is a diagram showing a storage area of a flash memory, and FIG. 3B is a diagram showing an address table.
An address table 27 can acquire a physical block address (PBA) with an index of a logical block address (LBA). The physical block address is an address on the flash memory for any corresponding erase block.
When a host or an application issues a command of accessing a block address of “0x55”, for example, the address is converted into “0x6B” using the address table, whereby access is made to the erase block 21 of the flash memory 20.
Under such memory management, data is updated on the flash memory as below.
1. A data-erased block 25 is prepared in advance for backup use with a physical address of “0xAA”.
2. Assuming that a logical block address “0x55” is addressed, a corresponding physical block address “0x6B” is acquired, and thus a page 22 in the block 21 is accessed. With such access, data of the block 21, i.e., a to-be-erased block, of the flash memory 20 is sequentially copied to the backup block 25 via a page buffer 24, which is separately provided.
3. For copying to-be-updated data of the page 22, any desired portion of the data is updated on the page buffer 24 before being copied to a target page 26.
4. After any available data of the page is completely copied, the address of the block 21 is exchanged to the address of the backup block 25 on the address table 27.
5. Lastly, the original block 21 is erased.
After such a procedure, for the logical block address “0x55”, an erase block corresponding to the physical block address “0xAA”, i.e., backup block 25, will be always accessed so that accessing remains consistent.
After a data update, the block 25 becomes accessible at the time of the above process 4 so that the time to be taken for block erasing can be saved.
If such a backup block is plurally provided and scattered throughout the storage area, intensive copying to any specific block is prevented. Moreover, address conversion as above serves well for the purpose of preventing access making to any defective block.
Patent Document 1 (JP-A-8-328762) describes the details about a management method for use in a WORM (write-once, read-many-times) system using address conversion on a page basis. The page here is a unit for batch writing of the flash memory.
FIGS. 4A and 4B are diagrams both showing a management method in the WORM system.
FIG. 4A is a diagram showing a storage area of a flash memory, and FIG. 4B is a diagram showing an address table.
With such a management method, a physical page address (PPA) can be acquired from an address table 28 with an index of a logical page address (LPA). The physical page address is an address on the flash memory for the corresponding page.
When a host issues a writing command to a logical page address of “0x5502”, for example, address conversion is performed using an address table on a page basis so that a physical page address “0x6B05” on the flash memory is acquired. As such, access is made to any corresponding area of the page 22 in the block 21.
For a data update in page 22, a search is made to find any appropriate free page area for direct data writing in the flash memory. As a writing destination considered appropriate, if a head page area 29 of the data-erased block 25 corresponding to a physical block address of “0xAA”, is selected only the data of the page 22 is updated via the page buffer 24, and thus updated data is written to the page area 29. At this time, the logical page address “0x5502” is remapped to a physical address “0xAA00” of the page area 29. The old data on the page 22 is left as it is for the time being but is made invalid.
With such memory management, as long as there is any free area in the flash memory, writing of only one-page data is needed for updating the respective page data.
Thus, this leads to data rewriting at high speed. During the data rewriting, there is no need for data erasing so that the rewriting frequency can be considerably reduced for the flash memory, and the useful life of the flash memory also can be increased.
The inventors of the invention have proposed the more advanced management technique utilizing address conversion on a page basis, e.g., JP-A-2005-114711, JP-A-2005-165234, and JP-A-2005-1714.
There is also the technique utilizing address conversion which is an intermediate version between a page-basis and a block-basis. For example, without changing the relationship between the blocks and the page groups in the blocks, the positional relationship between the pages inside of the blocks is remapped. The effects derived thereby for reduction of the overhead are intermediate in level between the above-described two techniques.
As such, by remapping using an address table, user data on the flash memory can be managed in various different manners.
With every such manner, the address table is referred to by using as an index the address value generated from the initial logical address, and information is acquired about the location of the corresponding user data, e.g., physical address on a flash memory. Based on the thus acquired location information, access is made to the data on the flash memory.
Especially, if every page group that is a unit for batch writing is subjected to remapping of changing their relative positions, the access efficiency can be increased with remarkable effects.